A portion of the disclosure recited in the specification contains material which is subject to copyright protection. Specifically, an Appendix in accordance with 37 CFR Section 1.96 is included which lists less than 10 pages of source code instructions for a process by which the present invention is practiced in a computer system. Appendix A comprises five pages. The copyright owner has no objection to the facsimile reproduction of the specification as filed in the Patent and Trademark Office. Otherwise, all copyright rights are reserved.
This invention generally relates to an apparatus and a method for estimating a frequency of an asynchronous signal being received at an input sample rate. More specifically, this invention relates to estimating, or tracking, an input sample frequency, and further provides a rate estimate of the input sample frequency for use in audio applications.
Many audio devices, such as computer sound cards and recording studio equipment, operate to receive, transmit, and manipulate audio information in a digital, rather than analog, form. Some audio sources, such as compact-disk players, Z-Video players, and digital video disks, generate a digital signal directly. Other audio sources, such as microphones, generate an analog signal, which can be converted to a digital signal with an analog-to-digital converter (xe2x80x9cADCxe2x80x9d). An ADC typically xe2x80x9csamplesxe2x80x9d the analog signal at a rate high enough to preserve the acoustic characteristics of the analog audio signal. Regardless whether the data is from a digital signal source or from an analog signal source (converted by an ADC), the data rate of the source may be different from the rate at which a digital audio device manipulates data. Digital audio devices that can receive digital data streams from a variety of sources at a variety of data rates often include digital sample rate converters that convert the input sample rate to an output sample rate that is compatible with the digital audio device.
Sample rate converters, whether digital, analog, or a combination thereof, may be considered either synchronous or asynchronous. A synchronous sample rate converter shares a common time base, or clock, with the input signal source. In order for a synchronous sample rate converter to operate, it must be able to lock to the clock signal used by the input device, and the input device must provide a clock output or a third device must provide a common clock output. An asynchronous sample rate converter does not require a common time base with the input signal source, and can accept input data from a wide variety of sources. Such asynchronous sample rate converters generally comprise a means (e.g., sample rate estimator) in which to first estimate the input sample rate or frequency of the stream of input data before frequency conversion proceeds. In operation, an asynchronous digital sample rate converter, for example, can convert between any two sample rates within the operating range of the converter, wherein the input sample rate is determined by a sample rate estimator.
One type of asynchronous digital sample rate converter takes an input sample stream, converts it to an analog signal with a digital-to-analog converter (DAC), and then converts that analog signal back to a digital signal at the desired output sample rate with an ADC. This approach is simple to understand and is direct, but is complex to implement and produces an inferior signal because of the distortion and noise that the A-to-D and D-to-A conversions add.
An alternative to asynchronous digital sample rate conversion is to use a phase-locked-loop approach. The phase-locked loop approach adapts the output data rate to the input data rate by adjusting the internal clock rate of the receiving device to the clock rate of the input device. The clock rate of the input device and the internal clock rate are both provided to a mixer, the mixer output, or product, is zero when the two rates are the same, and when the two clock rates are not the same, the mixer output is converted into a signal that adjusts the internal clock rate. This process can take several seconds to achieve lock and limits input data to those signals with a clock rate within the tuning range of the internal clock. The time-to-lock can be especially undesirable if the input clock rate is not constant, but drifts or otherwise changes. Another disadvantage of this approach is that, while the two clock rates are frequency matched, no phase relationship between the input and output data is maintained, which could lead to a loss of input data if the input data overwrites valid data. This also precludes the use of more than one asynchronous stream at a time, or mixing of a fixed-rate internal signal with the external asynchronous signal.
Many sample rate converters, including their constituent sample rate estimators, temporarily store the input data in a random-access memory (xe2x80x9cRAMxe2x80x9d), or other type of memory, to buffer the data while the sample rate estimation and conversion process proceeds. The RAM has a finite capacity and can not store an endless stream of input data; therefore, once an input value is read from a RAM address, that address becomes available for another input data point. FIG. 1 shows a simplified representation of a buffer 10 that is configured as a circle for illustrative purposes. Each segment 3 of the buffer represents an address where a data point may be written to or read from. The next input data point will be read into the buffer at the input data pointer location 5, writing over the value stored in that location, which has already been read. The next output data point will be read from the buffer at the output data pointer location 7. Both pointers will increment in the same direction around the buffer, represented by arrows, according to the input sample rate 9 and the output sample rate 11. The distance between the input pointer 5 and the output pointer 7 is represented as a phase angle 8. If the input sample rate suddenly increases, the input data pointer might overrun the output data pointer, writing over data that has not yet been read. In a phase-locked system that does not account for the phase relationship between the input data sample rate and the output data sample rate, small excursions in the input data sample rate might cause the input data pointer to overrun valid data in the buffer.
Therefore an asynchronous sample rate converter which achieves lock quickly and maintains an optimum input buffer configuration and signal fidelity is needed, wherein an apparatus and a method of estimating an actual input sample rate responds very fast to changes in the incoming frequency and can be made extremely accurate.
The present invention provides an apparatus and a method for estimating the sample rate of an asynchronous input, the apparatus and method for use in a digital device, such as a computing system, which responds very fast to changes in the incoming frequency and is extremely accurate.
Accordingly, in one embodiment, the present invention provides an asynchronous sample rate estimating apparatus having an internal data rate, wherein the apparatus comprises an input stage to receive a plurality of input data samples in a periodic data stream, the input stage configured to provide the plurality of input data samples and configured further to generate a phase error signal based upon later input data samples, a phase corrector configured to receive the phase error signal and a rate estimate signal to produce a phase correction signal, a reciprocal frequency error generator configured to receive a measured period and a current rate estimate to provide a reciprocal frequency error signal having a reciprocal frequency error signal amplitude, and a summing unit configured to receive the reciprocal frequency error signal and the phase correction signal and configured to provide a rate estimate correction signal, wherein the rate estimate correction signal is used to generate the new frequency estimate of the periodic data stream of input samples.
In another embodiment, the present invention provides an asynchronous sample rate estimating apparatus comprising a first-in-first-out buffer configured to receive input data at an input data rate, a write pointer configured to indicate a next data input position in the buffer, the write pointer configured to move to the next data input position at the input data rate, a read pointer configured to indicate a next data output position in the buffer, the read pointer configured to move to the next data output position according to a current rate estimate signal, a phase detector configured to provide a phase error signal, a reciprocal frequency error generator configured to receive a current rate estimate and a measured period to provide a reciprocal frequency error signal, a rate estimator configured to receive the reciprocal frequency error signal and a phase correction signal to provide a rate estimate signal, and a phase corrector configured to receive the phase error signal and the rate estimate signal to produce the phase correction signal, wherein the rate estimate signal is used to determine a frequency estimate of the input data rate.
In yet another embodiment, the present invention provides a method for estimating the frequency of an asynchronous signal comprising the steps of receiving a sampled asynchronous signal input, determining a measured sample period by evaluating a plurality of clock cycles between the sampled asynchronous signal input and a previously sampled asynchronous signal input, updating a reciprocal frequency error signal based upon a current rate estimate, generating a new phase correction signal based upon a rate estimate for centering a write pointer in a FIFO containing the sampled asynchronous signal input, and generating a rate estimate correction signal from the reciprocal frequency error signal and a current phase correction signal, where the current phase correction signal is based upon the new phase correction signal. In yet still another embodiment, the method further comprises the steps of adapting a current error gain to provide an error gain, and scaling the rate estimate correction signal to generate a new rate estimate step size, wherein the new rate estimate step size is used to approximate an estimated frequency to an actual frequency. Another embodiment of the present invention provides a method further comprising the steps of monitoring a system lock detector, and looping through the previous steps until a system lock is detected thus indicating the rate estimate is equivalent to the actual frequency.